1. Field of the Invention
The present invention relates generally to dual-port memories, and more specifically, to a dual-port memory including a random access memory connected to a first input/output port and a serial access memory connected to a second input/output port.
2. Description of the Background Art
FIG. 6 is a block diagram showing a structure of a conventional dual-port memory. In FIG. 6, provided on a semiconductor chip 1 are an address buffer 2, a row decoder 3, a column decoder 4, a sense amplifier group and input/output control circuit 5, a memory cell array 6, a transfer gate 7, a data register 8, a serial decoder 9, an address pointer 10, a data input/output buffer 11, a serial input/output buffer 12, and a timing generator 13. Timing generator 13 outputs various timing signals such as .phi.L, .phi.R, .phi.P, .phi.W, .phi.I and .phi.O based on externally applied various control signals such as a row address strobe signal RAS, a column address strobe signal CAS, a data transfer enable signal DTE, a shift control signal SC and a shift enable signal SE.
Address buffer 2 is provided with, for example, 9-bit address data A0-A8. Address buffer 2 latches row address data and column address data input in a time sharing manner in response to the timing signal .phi.L applied from timing generator 13. The row address data latched by address buffer 2 is applied to row decoder 3. The column address data latched by address buffer 2 is applied to column decoder 4. The column address data latched by address buffer 2 is also applied to address pointer 10.
Memory cell array 6 includes a plurality of word lines, a plurality of bit lines disposed crossing these word lines, and a plurality of memory cells arranged at the cross over points of the word lines and bit lines. Row decoder 3 selects one word line from the plurality of word lines in memory cell array 6, based on the row address data applied from address buffer 2. Sense amplifier group and input/output control circuit 5 includes a sense amplifier and an input/output control gate provided for every bit line in memory cell array 6. Column decoder 4 controls opening/closing of each input/output control gate based on the column address data applied from address buffer 20. Selection of a bit line is thus conducted. The input/output control gates in sense amplifier group and input/output control circuit 5 are connected to the first input/output port (hereinafter referred to as A port) through data input/output buffer 11.
The above-described address buffer 2, row decoder 3, column decoder 4, sense amplifier group and input/output control circuit 5, memory cell array 6 and data input/output buffer 11 constitute a random access memory (hereinafter referred to as RAM) to and from which writing and reading of data can be performed randomly.
Data register 8 includes a plurality of latch circuits arranged for the respective bit lines in memory cell array 6. The latch circuits connected in series constitute a so-called shift register. Transfer gate 7 controls data transmission between memory cell array 6 and data register 8 in response to the timing signal .phi.R applied from timing generator 3. Serial decoder 9 controls the shifting operation of data register 8 in response to pointer data applied from address pointer 10. Data register 8 is connected to the second input/output port (hereinafter referred to as B port) through serial input/output buffer 12. Serial input/output buffer 12 controls input/output of data between data register 8 and B port in response to the timing signals .phi.P, .phi.W, .phi.I and .phi.O applied from timing generator 13.
The above-described transfer gate 7, data register 8, serial decoder 9, address pointer 10 and serial input/output buffer 12 constitute a so-called serial access memory (hereinafter referred to as SAM). The SAM converts data of n rows read out en bloc from memory cell array 6 (data of 4 rows in the case of the dual-port memory shown in FIG. 6) into serial data, and outputs this serial data to B port. The SAM also converts externally input four pieces of serial data into parallel data of n rows and applies the same to memory cell array 6.
The dual-port memory shown in FIG. 6 has a structure of .times.4 bits. In other words, A port and B port each have four data input/output pins. A port is capable of inputting/outputting data DIO.sub.0 -DIO.sub.3 of 4 bits at a time. B port is capable of inputting/outputting four pieces of serial data SIO.sub.0 -SIO.sub.3 at a time.
FIG. 7 is a block diagram partially showing the structure of the dual-port memory shown in FIG. 6, especially the structure of the SAM in detail. As shown in FIG. 7, memory cell array 6 has four array blocks or sectors. It is therefore possible to read and write data of 4 bits at a time from and to memory cell array 6. Transfer gate 7, data register 8 and serial decoder 9 each include four sets of circuits. Serial input/output buffer 12 includes a serial preamplifier 121, a serial main amplifier 122 and a serial data-in-buffer 123. These serial preamplifier 122 and serial data-in-buffer 123 each include four sets of circuits. Serial preamplifier 121 has its operation controlled in response to the timing signals .phi.P and .phi.W applied from timing generator 13. Serial main amplifier 122 has its operation controlled in response to the timing signal .phi.O applied from timing generator 13. Serial data-in-buffer 123 has its operation controlled in response to the timing signal .phi.I applied from timing generator 13.
FIG. 8 is a timing chart showing the operation of the dual-port memory shown in FIGS. 6 and 7 at the time of serial read transfer. FIG. 9 is a timing chart showing the operation of the dual-port memory shown in FIGS. 6 and 7 at the time of serial write transfer. The term "serial read transfer" means a mode in which the SAM converts data of four rows read out from the memory cell array 6 of the RAM into serial data and outputs the same. "Serial write transfer" is a mode in which the SAM converts externally input four pieces of serial data into parallel data of four rows and transfers the same to memory cell array 6.
Referring to FIG. 8, the operation at the time of serial read transfer will be described. The row address strobe signal RAS is pulled to L level. In response to this, the timing signal .phi.L applied from timing generator 13 to address buffer 2 is activated, and address buffer 2 latches row address data. The row address data latched by address buffer 2 is applied to row decoder 3. Row decoder 3 decodes the applied row address data and selects a row corresponding to each array block in memory cell array 6. Memory cell array 6 as described above has four array blocks, and, therefore, four word lines are selected at a time for memory cell array 6 as a whole. Data stored in memory cells belonging to the selected word lines is read out to bit lines in memory cell array 6. Then, with the data transfer enable signal DTE being pulled to H level, the timing signal .phi.R is pulled to H level. Transfer gate 7 transfers the data of four rows read out from memory cell array 6 to data register 8 in response to the timing signal .phi.R being pulled to H level.
Data register 8 outputs serially the held data of four rows. Data register 8 has four circuits each capable of holding data of one row, and outputs from these circuits are applied to serial buses SB.sub.0 -SB.sub.3, respectively.
Serial preamplifier 121 is activated in response to the timing signal .phi.P which is in synchronization with the serial control signal SC. At the time, serial preamplifier 121 is activated in synchronization with the shifting operation of data register 8 and amplifies serial signals serially output from data register 8. Four serial signals amplified by serial preamplifier 121 are applied to serial main amplifier 122 through internal serial buses ISB.sub.0 -ISB.sub.3. Serial main amplifier 122 amplifies the four serial signals applied from serial preamplifier 121 in response to the timing signal .phi.O which is in synchronization with the serial control signal SC. The four serial signals amplified by serial main amplifier 122 are output to B port as serial data SIO.sub.0 -SIO.sub.3.
Referring to FIG. 9, the operation of the conventional dual-port memory shown in FIGS. 6 and 7 at the time of its serial write transfer will be described. The row address strobe signal RAS is pulled to L level. In response to this, address buffer 2 latches the row address data. Row decoder 3 decodes the row address data latched in address buffer 2 and selects the word line of a corresponding row in each array block in memory cell array 6. Memory cells belonging to f our word lines selected at that time allow writing of data transferred from the SAM.
B port is provided with the external four pieces of serial data SIO.sub.0 -SIO.sub.3. Serial data-in-buffer 123 amplifies four serial signals input from B port in response to the timing signal .phi.I which is in synchronization with the serial control signal SC and outputs the amplified signals to internal serial buses ISB.sub.0 -ISB.sub.3. At that time, the timing signal .phi.O is in the L level, and serial main amplifier 122 is deactivated. Serial preamplifier 121 operates in response to the timing signal .phi.W which is in synchronization with the serial control signal SC. At that time, the serial preamplifier 121 connects internal serial buses ISB.sub.0 -ISB.sub.3 and serial buses SB.sub.0 -SB.sub.3 if the timing signal .phi.W is in H level. However, serial preamplifier 121 outputs the input serial signals to serial buses SB.sub.0 -SB.sub.3 without amplifying these signals. This is because the externally input serial data is written into memory cells after being amplified in sense amplifier group and input/output control circuit 5 at the time of data writing, and it is not particularly necessary to amplify the data at serial preamplifier 121. The four serial signals output from serial preamplifier 121 are applied to data register 8 through serial buses SB.sub.0 -SB.sub.3.
Then, the data transfer enable signal DTE is pulled to H level, and the timing signal .phi.R is pulled to H level. This causes the data of four rows held in data register 8 to be transferred to memory cell array 6. At that time, memory cells of four rows are selected in each array block in memory cell array 6, and, therefore, the applied data is written into the memory cell array of these four rows.
A conventional dual-port memory structured as described above has a number of serial data input/output pins in each SAM, and requires a large circuit area for serial main amplifier 122 and serial data-in-buffer 123 in serial input/output buffer 120. For example, in a dual-port memory of .times.4 bit structure shown in FIGS. 6 and 7 must be provided with four serial data input/output pins at B port. Serial main amplifier 122 and serial data-in-buffer 123 each require four sets of circuits for processing four serial signals.